VHDL Snippets

Entity

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entity ENTITY_NAME is
port(
i_a : in std_logic;
i_b : in std_logic;
i_c : in std_logic;
o_c : out std_logic
);
end entity;

Architecture

Processes run concurrent to each other.

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architecture ARCHITECTURE_NAME of ENTITY_NAME is
type states is (q0, q1, q2, q3);
signal state : states; -- end internal signals

begin
-- concurrent code
PROCESS_NAME : process(i_c) -- sensitivity list
begin
if rising_edge(i_c) then
-- sequential code
elsif falling_edge(i_c) then
-- sequential code
end if;
end process;
-- concurrent code
end architecture;

Process

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process(c_in) is
begin
if (c_in='1') then
-- do something
end if;
end process;

Process (rising edge)

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process(c_in) is
begin
if (c_in'event and c_in='1') then
-- do something
end if;
end process;