VHDL Snippets

Dec 03, 2011 in Programming

Entity

entity ENTITY_NAME is
port(
    i_a : in std_logic;
    i_b : in std_logic;
    i_c : in std_logic;
    o_c : out std_logic
);
end entity;

Architecture

Processes run concurrent to each other.

architecture ARCHITECTURE_NAME of ENTITY_NAME is
type states is (q0, q1, q2, q3);
signal state : states; -- end internal signals

begin
-- concurrent code
PROCESS_NAME : process(i_c …
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