XML Introduction

A XML (short for Extensible Markup Language) document consists of:

  • the prolog (optional)
  • the document type definition (DTD, optional)
  • the root element (which furthermore consists of more elements, tree structure)

Comments and processing instructions can be defined outside of tags.

Prolog

The basic prolog looks like this: <?xml version="1.0" ?> An extended version: <?xml version="1.0" encoding="ISO-8859-1" standalone="yes" ?>

Attributes explained:

  • version: XML version
  • encoding: Character set, defaults to UTF-8
  • standalone: define if extern entities or DTDs are being referenced in this document

Document Type Definition

The DTD defines structure validation rules for our documents. We fundamentally construct elements with their respective type (analogous to the database schema).

Reasons to use DTD:

Quick Introduction to C

C Preprocessor

C preprocessor code will be executed before compiling the actual c code.
Preprocessor lines start with # and do not end with a semicolon (in contrast to usual code instructions).

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#define MAX_SIZE = 1
#undef MAX_SIZE

The first instruction replaces instances of MAX_SIZE with 1. The second instruction undefines the previous made call.

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#include <stdio.h>
#include "myheader.h"

Tells the cpp to include stdio.h from the system libraries, where else the next line includes the header file myheader.h from the local directory.

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#ifndef MAX_SIZE
...
#endif

#ifdef DEBUG
...
#endif

Pointers

A pointer points to a variable address/stores a variable address.

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char val = 'c';
char val2;
char *pointer = &amp;val;
val2 = *pointer;

VHDL Snippets

Entity

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entity ENTITY_NAME is
port(
i_a : in std_logic;
i_b : in std_logic;
i_c : in std_logic;
o_c : out std_logic
);
end entity;

Architecture

Processes run concurrent to each other.

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architecture ARCHITECTURE_NAME of ENTITY_NAME is
type states is (q0, q1, q2, q3);
signal state : states; -- end internal signals

begin
-- concurrent code
PROCESS_NAME : process(i_c) -- sensitivity list
begin
if rising_edge(i_c) then
-- sequential code
elsif falling_edge(i_c) then
-- sequential code
end if;
end process;
-- concurrent code
end architecture;

Process

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process(c_in) is
begin
if (c_in='1') then
-- do something
end if;
end process;

Process (rising edge)

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process(c_in) is
begin
if (c_in'event and c_in='1') then
-- do something
end if;
end process;