VHDL Snippets

Entity

1
2
3
4
5
6
7
8
entity ENTITY_NAME is
port(
i_a : in std_logic;
i_b : in std_logic;
i_c : in std_logic;
o_c : out std_logic
);
end entity;

Architecture

Processes run concurrent to each other.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
architecture ARCHITECTURE_NAME of ENTITY_NAME is
type states is (q0, q1, q2, q3);
signal state : states; -- end internal signals

begin
-- concurrent code
PROCESS_NAME : process(i_c) -- sensitivity list
begin
if rising_edge(i_c) then
-- sequential code
elsif falling_edge(i_c) then
-- sequential code
end if;
end process;
-- concurrent code
end architecture;

Process

1
2
3
4
5
6
process(c_in) is
begin
if (c_in='1') then
-- do something
end if;
end process;

Process (rising edge)

1
2
3
4
5
6
process(c_in) is
begin
if (c_in'event and c_in='1') then
-- do something
end if;
end process;
1
2
3
4
5
6
process(c_in) is
begin
if (rising_edge(c_in)) then
-- do something
end if;
end process;

Component

1
2
3
4
5
6
7
8
9
10
architecture ARCHITECTURE_NAME of ENTITY_NAME is
component HALF_ADDER
port (i_x, i_y, i_enable : in std_logic;
o_result, o_carry : out std_logic );
end component;

begin
HA1 : half_adder port map (i_x => a, i_y => b, i_enable => i_enable, o_result => s1, o_carry => c1);
HA2 : half_adder port map (s1, cin, i_enable, sum, c2); -- defining through order of ports
end architecture;

Using a Component

1
2
HA1 : half_adder port map (i_x => a, i_y => b, i_enable => i_enable, o_result => s1, o_carry => c1);
HA2 : half_adder port map (s1, cin, i_enable, sum, c2); -- defining through order of ports

Variables

Sequential, repeated assignments allowed (e.g. in loops).

1
2
variable test : std_logic;
variable := '1';

Signals

Concurrent, no repeated assignments allowed within a segment.

1
2
signal test : std_logic;
signal <= '1';

Bit Vector

1
2
3
bit_vector : std_logic_vector(1 downto 0);
bit_vector <= "00";
bit_vector'range -- to get the length

Enumeration

1
2
type state_type is (state1, state2, state3);
signal state : state_type;

Initial Values

1
2
constant value_one : std_logic_vector(5 downto 0) := “100000”; -- not ignored in actual hardware
signal value_two : std_logic_vector(5 downto 0) := “100000”; -- will be ignored outside simulations

Solution: initialize values in reset segment!

1
2
3
if reset = '1' then
value_one <= "1000000";
end if;

Case

1
2
3
4
5
6
7
8
case expression is
when choice =>
-- sequence of statements
when choice2 =>
-- sequence of statements
when others =>
-- optional default case
end case;

Functions

1
2
3
4
5
function FUNCTION_NAME (parameter : parameter_type) return type is
-- declarations
begin
-- sequential code
end function;

Comments